The present disclosure relates to a solid-state imaging device, a method of manufacturing the solid-state imaging device, and an electronic apparatus, and, particularly to, a solid-state imaging device, of which the height can be decreased, a method of manufacturing the solid-state imaging device, and an electronic apparatus.
Up to now, in an electronic apparatus which includes an imaging function, such as a digital still camera or a digital video camera, for example, a solid-state imaging device, such as a Charge Coupled Device (CCD) or a Complementary Metal Oxide Semiconductor (CMOS) image sensor, has been used. The solid-state imaging device includes photodiodes (PDs) that perform photoelectric conversion, and pixels in which a plurality of transistors are combined. An image is constructed based on pixel signals which are output from a plurality of pixels arranged in a planar manner.
In addition, a CMOS image sensor according to the related art is driven using a rolling shutter method of reading the pixel signals sequentially for each pixel row by transmitting electrical charge from the PDs. In contrast, in recent years, a CMOS image sensor has been developed which can be driven by a global shutter method of reading the pixel signals sequentially for each pixel row by transmitting an electrical charge from the entire PDs at approximately the same timing and holding the electrical charge in the memory sections which are provided for the respective pixels. In such a CMOS image, a light shielding property is necessary for the memory sections which are formed on a silicon substrate.
In contrast, a solid-state imaging device that has a structure, in which a photoelectric conversion film (for example, CuInGaS2 (Copper Indium Gallium DiSelenide (CIGS)) film) is laminated on the silicon substrate on which the PDs are formed, has been developed (refer to Japanese Unexamined Patent Application Publication No. 2012-64822 and Japanese Unexamined Patent Application Publication No. 2013-26332).